Vegapunk: Accurate and Fast Decoding for Quantum LDPC Codes with Online Hierarchical Algorithm and Sparse Accelerator

Review Form

Reviewer: The Guardian (Adversarial Skeptic)

Summary

The authors present "Vegapunk," a software-hardware co-design framework for decoding quantum Low-Density Parity-Check (qLDPC) codes. The core proposal involves an offline, SMT-based strategy to transform a given check matrix into a partially block-diagonal form, purportedly to mitigate quantum degeneracy. This is followed by an online, hierarchical greedy algorithm, implemented on a custom FPGA accelerator, to perform the decoding under a real-time (<1µs) latency constraint. The authors claim that this approach achieves decoding accuracy on par with the state-of-the-art BP+OSD decoder while meeting the strict latency requirements for fault-tolerant quantum computing.

Strengths

1. The work addresses the critical and well-understood trade-off between accuracy and latency in qLDPC decoding, a central challenge for the field.
2. The software-hardware co-design approach is a logical direction for tackling this problem, correctly identifying that algorithmic improvements must be paired with dedicated hardware to meet real-time constraints.
3. The use of an offline pre-computation step to simplify the online decoding problem is a sound principle.

Weaknesses

My primary concerns with this submission relate to the feasibility of the offline step, the significant limitations of the online greedy heuristic, and the overstatement of the empirical results.

1. Computational Feasibility of SMT-based Decoupling: The paper's proposal hinges on an offline SMT optimization to find suitable transformation (T) and permutation (P) matrices (Section 4.2, page 5). The authors claim this "only needs to be performed once per check matrix" (page 6) but provide no data on the computational cost of this step. The search space for these matrices is combinatorially vast, and solving such an SMT problem is likely NP-hard. It is entirely plausible that this offline step is computationally intractable for the very codes for which this decoder is intended. Without reporting the wall-clock time required by the Z3 solver for the benchmarked codes (especially [[784,24,24]]), the entire method's practicality is unsubstantiated.

2. Fundamentally Limited Greedy Heuristic: The online hierarchical algorithm is a greedy search that is hard-capped at a maximum iteration count of M=3 (Section 6.4, page 12). This explicitly limits the search for the "right error" (r) to a maximum Hamming weight of 3. This is a severe and arbitrary constraint. While low-weight errors are most probable, error correction codes are defined by their ability to correct errors up to a certain weight ((d-1)/2). By design, this decoder will fail on any valid correctable error pattern that requires a right-part error of weight 4 or more. Claiming accuracy "on par with BP+OSD" (a far more exhaustive search method) is therefore a significant overstatement. The justification provided in Figure 13 (page 13) merely shows diminishing returns for their specific heuristic; it does not prove that higher-weight errors are irrelevant.

3. Unsupported Complexity Claims vs. Implementation: The complexity analysis (Section 4.4, page 8) claims logarithmic scaling with sufficient parallelism, suggesting P > n*K parallel processing units. For the [[784,24,24]] code, this implies P > 3920 * 14 ≈ 55,000 units. It is highly doubtful that the FPGA implementation reported in Table 4 (page 12) instantiates this many parallel cores. The paper fails to state how many parallel HDUs were actually implemented, creating a disconnect between the theoretical scaling argument and the physical reality of the accelerator that produced the results. The reported latency is likely for a configuration with far less parallelism, rendering the O(log n + S) complexity claim moot.

4. Inconsistent Evaluation and Misleading Comparisons:

   • Accuracy: The LER plots in Figure 10 (page 10) show that Vegapunk is frequently outperformed by the BP+OSD-CS(7) baseline, especially at lower physical error rates which are the target regime for fault tolerance (e.g., plots a1, a3). The claim of being "on par" is not supported by the authors' own data; in several key instances, there is a clear accuracy penalty.
   • Noise Models: The evaluation employs a circuit-level noise model for BB codes but a less realistic phenomenological noise model for HP codes (Section 6.1, page 10). This inconsistency undermines the generality of the conclusions and prevents a fair comparison of performance across the different code families. A rigorous evaluation requires a consistent and realistic noise model for all tested codes.

Questions to Address In Rebuttal

1. Regarding the offline SMT decoupling (Section 4.2): What is the actual wall-clock time required by the Z3 solver for the largest codes presented, namely [[784,24,24]] and [[1488,30,7]]? Please provide evidence that this offline step is computationally feasible for codes relevant to fault-tolerant computing.

2. The online algorithm is limited by M=3, capping the searchable Hamming weight of the "right error" to 3. Please provide a rigorous justification for why this hard limit does not unacceptably compromise decoding accuracy. What is the fraction of correctable errors (within the code's distance) that are missed due to this constraint, and how does this affect the error floor?

3. The parallel complexity analysis (Section 4.4) relies on a number of parallel units (P) that appears unrealistic for an FPGA implementation. Please clarify the exact number of parallel Hierarchical Decoding Units (HDUs) instantiated in the evaluated FPGA design for each code. How does the latency scale if the number of HDUs is fixed while the code size n increases?

4. In several plots in Figure 10 (e.g., a1 for [[72,12,6]] and a3 for [[108,8,10]]), Vegapunk's Logical Error Rate is visibly higher than that of BP+OSD-CS(7). How do the authors reconcile this observable accuracy gap with the claim of being "on par" with the state-of-the-art?

5. Please justify the use of two different noise models (circuit-level for BB codes, phenomenological for HP codes). Would the conclusions for HP codes remain the same if a more realistic circuit-level noise model were applied?

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Review Form

Reviewer: The Synthesizer (Contextual Analyst)

Summary

This paper presents "Vegapunk," a comprehensive software-hardware co-design framework aimed at solving the critical accuracy-latency tradeoff in the decoding of quantum Low-Density Parity-Check (qLDPC) codes. The central challenge in this domain is that fast decoders like Belief Propagation (BP) are inaccurate due to issues like quantum degeneracy, while accurate decoders like BP with Ordered Statistics Decoding (BP+OSD) are far too slow for the real-time requirements of fault-tolerant quantum computers (typically < 1µs).

Vegapunk's core contribution is a novel two-pronged strategy:

1. Offline SMT-Optimized Decoupling: The authors reframe the problem by performing a one-time, offline transformation of the qLDPC check matrix. Using a Satisfiability Modulo Theories (SMT) solver, they find a transformation that converts the wide, unstructured check matrix into a more manageable form: a series of smaller, independent diagonal blocks and a sparse residual matrix. This pre-computation directly mitigates the quantum degeneracy issue that plagues BP, fundamentally simplifying the online decoding task.

2. Online Hierarchical Greedy Algorithm & Accelerator: The structured matrix produced by the offline step enables a much simpler online decoding algorithm. Instead of complex message passing, Vegapunk uses a hierarchical, greedy search to find the most likely error pattern. The authors then design a dedicated, sparse hardware accelerator that fully exploits the parallelism and sparsity inherent in this new algorithmic structure, allowing it to meet the stringent real-time deadline.

Experimental results demonstrate that Vegapunk achieves decoding latencies under 1µs for significant qLDPC codes (up to [[784,24,24]]) while maintaining a logical error rate comparable to the highly accurate but slow BP+OSD, effectively breaking the existing tradeoff.

Strengths

1. High Conceptual Significance and Impact: This work addresses what is arguably one of the most significant architectural bottlenecks for next-generation quantum computers. The field has largely acknowledged that surface codes have poor scaling overhead, and qLDPC codes are the leading contender to replace them. However, the lack of a practical, real-time decoder has been the primary barrier to their adoption. By providing a plausible and well-evaluated solution that achieves both speed and accuracy, this work could fundamentally alter the trajectory of quantum architecture research, shifting focus toward the practical implementation of these more efficient codes.

2. Novel and Elegant Problem Reframing: The most intellectually compelling aspect of this paper is the offline decoupling strategy (Section 4.2, page 5). The application of SMT solvers—a tool from the formal methods and verification community—to restructure a coding theory problem is a brilliant piece of interdisciplinary thinking. It transforms a difficult, recurring online problem into a (potentially very hard) one-time offline problem and a much simpler online one. This "pre-computation" approach is an elegant way to manage complexity and is a powerful design pattern that could inspire solutions in other areas.

3. Holistic Full-Stack Approach: The authors demonstrate a mature understanding of the problem by providing a full-stack solution. They do not merely propose a new algorithm in isolation; they consider its hardware mapping from the outset. The co-design of the hierarchical algorithm with the sparse accelerator (Section 5, page 8) is crucial. This demonstrates a deep appreciation for the fact that in the realm of quantum computer architecture, algorithms and hardware are inextricably linked. This end-to-end perspective, from abstract matrix transformation to FPGA implementation details, makes the work far more credible and impactful.

4. Strong and Well-Contextualized Empirical Evaluation: The experimental results are thorough and convincing. The authors benchmark against the correct state-of-the-art baselines (BP for speed, BP+OSD for accuracy) using relevant and challenging qLDPC code families (BB and HP codes). The demonstration of sub-microsecond latency for a large [[784,24,24]] code is a headline result that will capture the community's attention. The LER curves in Figure 10 (page 10) clearly show that they have achieved their goal of matching BP+OSD's accuracy, solidifying their central claim.

Weaknesses

While the core idea is powerful, the paper could be strengthened by addressing the broader implications and potential limitations of its approach.

1. Scalability and Cost of the Offline Step: The SMT-based decoupling is the "secret sauce," but the paper provides limited discussion on the practical cost of this step. SMT problems can have exponential complexity. While performing a difficult computation offline is acceptable, it is crucial to understand its limits. How long did the Z3 solver take for the [[784,24,24]] code? How will this scale to the even larger codes required for full-scale fault tolerance? A discussion of the computational complexity and resource requirements of the offline step would provide a more complete picture of the framework's practicality for future codes.

2. Generality of the Decoupling Strategy: The method is demonstrated successfully on BB and HP codes. The authors provide some intuition for why a block-diagonal structure can be found for these specific code families (Section 4.2, "Caveats of Check Matrix Decomposition," page 6). However, the broader applicability of this SMT formulation to any arbitrary qLDPC code remains an open question. Is there a risk that for some code families, the SMT solver might fail to find a useful, sparse decomposition? A more general discussion on the conditions under which this method is expected to succeed would be valuable.

3. Limited Intuition on the Online Heuristic: The online algorithm is a greedy search with a very small maximum iteration count (M=3). The ablation study in Figure 13 (page 13) empirically justifies this choice by showing diminishing returns. However, the paper could offer a deeper theoretical or intuitive explanation for why such a simple heuristic is so effective. Is it purely that most correctable errors have low weight, or does the SMT decoupling process structure the problem in such a way that the residual syndrome becomes "easy" to solve greedily? Connecting the success of the online algorithm more explicitly to the properties of the offline transformation would strengthen the narrative.

Questions to Address In Rebuttal

1. Could the authors please provide data on the runtime and resource usage of the offline SMT decoupling step for the largest codes tested? What are their projections for how this offline cost will scale as qLDPC codes grow in size in the future?

2. Can the authors comment on the expected generality of their SMT-based decoupling? Are there known properties of qLDPC check matrices (e.g., related to their construction) that would make them more or less amenable to this transformation?

3. The success of the simple, low-iteration greedy search is a key enabler for the framework's speed. Could the authors provide more intuition as to why this approach is sufficient? Does the offline decoupling effectively "pre-solve" the hardest parts of the problem, leaving a residual search space that is easily navigable by a greedy algorithm?

4. On a lighter note, is there a specific inspiration behind the name "Vegapunk"? It is a distinctive and memorable choice.

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Review Form

Reviewer: The Innovator (Novelty Specialist)

Summary

This paper, "Vegapunk," presents a software-hardware co-design framework for decoding quantum Low-Density Parity-Check (qLDPC) codes. The authors claim to achieve both high accuracy (comparable to BP+OSD) and low, real-time latency (< 1µs), addressing a well-known trade-off in the field. The central thesis is that a computationally intensive offline pre-processing step can transform the qLDPC check matrix into a structure that enables a very simple, fast, and parallelizable online decoding algorithm.

The core of the proposed novelty lies in using Satisfiability Modulo Theories (SMT) solvers to perform this offline matrix transformation. This "decoupling" yields a matrix with a block-diagonal structure and a sparse remainder. The online decoding algorithm is a hierarchical, greedy search that first guesses the error components corresponding to the sparse part of the matrix and then directly solves for the errors related to the block-diagonal part. A dedicated accelerator is designed to be a direct hardware mapping of this online algorithm.

While the constituent concepts (greedy algorithms, matrix transformations, hardware acceleration) are not new in isolation, their synthesis, particularly the use of an SMT solver to find an optimal matrix structure for decoding, appears to be a genuinely novel approach in this domain.

Strengths

1. Novel Offline Formulation: The primary and most significant novel contribution is the offline, SMT-optimized decoupling strategy (Section 4.2, page 5). While SAT/SMT solvers have been explored in classical coding theory for tasks like finding minimum-weight codewords, their application here is fundamentally different and new. The authors are not using the SMT solver to decode, but rather to restructure the decoding problem itself. Formulating the search for optimal transformation (T) and permutation (P) matrices as a constrained optimization problem for an SMT solver (Figure 5, page 5) is a clever and, to my knowledge, unprecedented method for preparing a qLDPC code for hardware-accelerated decoding.

2. Synergistic Algorithm-Architecture Co-Design: The novelty is reinforced by the tight coupling between the offline transformation and the online algorithm. The online hierarchical greedy algorithm (Section 4.3, page 6) is specifically enabled by the structure created by the SMT solver. While greedy search is a standard heuristic, its application here—guessing the "right error" r to simplify the solution for the "left error" l—is a direct consequence of the D' = ([diag(D_i)], A) decomposition. This demonstrates a strong system-level novelty where the offline step creates a problem that the simple online step is uniquely suited to solve.

3. Complexity Shifting as an Architectural Principle: The work presents a clear and novel architectural trade-off: shifting immense computational complexity from the time-critical online path to a one-time, offline pre-computation. This is a powerful design pattern, and its application to the qLDPC decoding problem appears to be a new and insightful contribution.

Weaknesses

My concerns are not that the core idea has been done before, but rather with the characterization and evaluation of the novel components themselves.

1. Under-explored Scalability of the Core Novelty: The central claim hinges on the offline SMT step, yet the paper provides zero data on its computational cost. SMT is NP-hard. The "Caveats of Check Matrix Decomposition" section (page 6) briefly discusses the process but completely omits any discussion of the SMT solver's runtime. How long did it take to find the transformation matrices for the [[784,24,24]] BB code? Hours? Days? Weeks? Does the solver time scale polynomially or exponentially with the code size? Without this information, the practicality of the entire approach for future, much larger qLDPC codes remains a major open question. The novelty is significant, but its viability is not established.

2. Limited Generalizability of the Novel Method: The SMT formulation is evaluated only on highly structured Bivariate Bicycle (BB) and Hypergraph Product (HP) codes. As noted on page 6, the structure of these codes provides hints for the decomposition (e.g., K = max(min(l, m), l x m) for BB codes). It is unclear whether the SMT-based approach is a general tool or if its success is an artifact of the inherent algebraic structure of these specific code families. A truly novel method should demonstrate robustness on less structured or more generic qLDPC code constructions.

3. Incremental Novelty of the Online Algorithm: The online hierarchical algorithm, when viewed in isolation, is a simple greedy search. Its novelty is almost entirely derived from the pre-transformed matrix it operates on. Conceptually, the strategy of guessing a small number of error bits to resolve a syndrome is related to the post-processing in Ordered Statistics Decoding (OSD) or decimation strategies used in other decoders (e.g., BPGD). The paper should more clearly articulate the fundamental delta between its "guess-and-solve" method and these prior conceptual frameworks, beyond simply stating that it operates on a different matrix structure.

Questions to Address In Rebuttal

The authors should address the following points to solidify the significance of their novel contributions:

1. Scalability of the SMT Solver: Please provide the runtime of the Z3 SMT solver for the largest BB code ([[784,24,24]]) and the largest HP code ([[1488,30,7]]) presented in the paper. Can you provide any data or theoretical arguments regarding how this runtime scales with n (number of qubits)?

2. Generalizability: Have you attempted to apply your offline SMT decoupling strategy to other families of qLDPC codes that lack the clean algebraic structure of BB or HP codes? If the method failed or was too slow, this would be crucial information for understanding the boundaries of this novel technique.

3. Algorithmic Distinction: Please provide a more detailed comparison between the online hierarchical algorithm and decimation-based approaches like BPGD [48]. Both involve iteratively making high-confidence "guesses" to simplify the remaining problem. What is the fundamental algorithmic innovation in your online approach beyond the fact that it leverages the pre-computed matrix structure?